1. Field of the Invention
The present invention relates to the field of computer memory. More particularly, the present invention relates to a method and structure for placing charge onto the floating gate of a non-volatile memory element while drawing low levels of current.
2. Art Background
Flash memory refers to one type of erasable and electrically programmable read-only memory (EEPROM) which uses MOS transistors that include electrically isolated gates referred to as floating gates. An illustrative diagram is shown in FIG. 1. The memory cell 10 includes a drain region 15 and a source region 20 in a substrate 23. The source region 20 and drain region 15 are asymmetrically doped. A polysilicon floating gate 25 is generally disposed above and between these regions and insulated from these regions by an insulating layer. The floating gate 25, at completion of processing, is completely surrounded by insulating layers and hence electrically floats. A second gate referred to as the control gate 30 is disposed above the floating gate and is fabricated from a second layer of polysilicon. The second insulating layer separates the floating gate 25 from the control gate 30.
Typically the flash memory cells are programmed by hot electron injection. As electrons are attracted and captured onto the floating gate, the threshold voltage of that memory cell is altered. The threshold voltage is defined to be the minimum amount of voltage that must be applied to the control gate before the memory cell is "turned on" to permit conduction between the cell's source and drain regions. The threshold voltage characteristics of a memory cell are controlled by the amount of charge that is retained on the floating gate of the memory cell.
Referring to FIG. 2, the memory cells are programmed (by negatively charging the floating gate) by connecting the control gate programming potential of approximately 12 volts, the drain region to a drain programming potential of approximately 6 volts and the source region to ground. Under these conditions, electrons are collected on the floating gate causing the threshold voltage of the memory cell to rise. When this occurs, the memory cell is said to have a programmed threshold voltage V.sub.tp.
To erase the cell, the drain region is floated, the control gate is grounded and an erasure potential of approximately 12 volts is applied to the source region. Alternatively, the source voltage may be lowered to approximately 5 V and a negative voltage of approximately -8 V is applied to the control gate. Under these conditions, electrons tunnel from the floating gate to the source region. This removes the electrons deposited on the floating gate of the memory cell, causing the threshold voltage of the memory cell to decrease. The memory cell is then said to have an erase threshold voltage V.sub.te.
To read the memory cell, a positive read potential less than that which would cause electron transfer onto the floating gate, for example, 5 volts, is supplied to the control gate. A potential, for example, 1 volt, is also supplied to the drain region and the source is grounded. The amount of current flowing through the device is sensed to determine if the floating gate is charged with electrons, indicating that the memory cell has been programmed.
One disadvantage of prior flash EPROMs is that the drain current utilized during the program operation is quite high, for example, 800 microamps. The relatively high quantity of current renders it difficult to provide programming voltage from charge pumps located on the component. Furthermore, the amount of current limits the number of flash cells that can be programmed in parallel as only a limited amount of current is available at any one time. Simply lowering the current utilized may be performed; however, the lower current drastically increases the amount of time needed to program memory cells. Furthermore, the size of the drain select device is determined by the maximum current required by the cell during programming, thus lowering the programming current reduces the size of the drain select device.
Multilevel Flash EEPROM cells (MLC) are a promising approach to allow an increased amount of information to be stored. In a MLC component, each memory cell can store one of a plurality of concentrations of electrons on the floating gate, enabling each cell to store one of a plurality of threshold voltages and therefore provide additional information in each cell. However, a MLC must be precisely programmed to properly delimit the different quantities of electrons the floating gate can store. This is a slow process since the Vt of the flash cell is adjusted slowly in order to precisely generate the desired threshold voltage value. To offset the overall amount of time required to program an array of MLCs, it is desirable to program a number of cells in parallel. However, the amount of current required is multiplied by the number of cells to be programmed in parallel. Therefore, if the individual cell current can be reduced during placement of the threshold voltages on the MLC, then more cells can be programmed in parallel, thereby improving the programming performance.